Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses
Electrostatic discharge (ESD) is still a challenging reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, it has been common to integrate multiple separated power domains into a single chip for power manage...
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Veröffentlicht in: | IEEE transactions on electron devices 2021-04, Vol.68 (4), p.1461-1470 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | Electrostatic discharge (ESD) is still a challenging reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, it has been common to integrate multiple separated power domains into a single chip for power management or noise isolation considerations. Besides, the fabricated transistors with thinner gate oxide for high-speed operation cause the ICs more sensitive to charged-device model (CDM) ESD events, especially under cross-domain stresses. The traditional cross-domain CDM ESD protection would result in some restrictions on circuit applications or cause some performance degradation. Thus, a new protection design with stacking footer/header metal-oxide-semiconductor (MOS) structure against cross-domain CDM ESD stresses was proposed in this work and verified in 0.18- \mu \text{m} CMOS technology. The proposed design got higher ESD robustness under CDM and HBM (human body model) ESD tests. Moreover, the CDM robustness of different stacking-MOS protection designs was also investigated in detail. |
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ISSN: | 0018-9383 1557-9646 |
DOI: | 10.1109/TED.2021.3061325 |