Investigation of Trap-Induced Threshold Voltage Instability in GaN-on-Si MISHEMTs

It is shown that an E_{\rm C} -0.90 eV trap in commercial AlGaN/GaN MISHEMTs grown on a Si (111) substrate is responsible for a −1.8-V threshold voltage ( V_{\rm T} ) instability using a combination of defect spectroscopy and double-pulsed current-voltage measurements. The E_{\rm C} -0.90 eV trap is located in the GaN buffer and is emptied by high drain biases in pinch-off, which raises the trap above the Fermi level in the GaN buffer. This trap also exhibits both fast and slow recovery processes that are explained by the availability of free electrons throughout the depth of the GaN buffer and the trapping process that depletes the free electron concentration. TCAD modeling is used to demonstrate this process and also to show why there is not a significant increase in buffer leakage current after the large negative V_{\rm T} shift due to this trap. This demonstrates that optimizing buffer designs are critical for ideal device performance.