Tunneling Negative Differential Resistance-Assisted STT-RAM for Efficient Read and Write Operations

The adoption of spin-transfer torque random access memory (STT-RAM) into nonvolatile memory systems faces three major obstacles: high write energy, low sensing margin, and high read disturbance. Many designs have been suggested to resolve each of these challenges separately and at the cost of significant overhead. We propose a single low-overhead solution to all these problems without changing the underlying memory architecture by using negative differential resistance devices like tunnel diodes or tunnel field-effect transistors to assist the STT-RAM write and read process. We show through simulations that the proposed designs can dramatically improve the write and read energy efficiency and sensing margins while minimizing the read disturbance, even after accounting for process variations. Our results open a design path for energy-efficient and reliable STT-RAM technologies.