Chord-Fractal Capacitor in CMOS Technology

The proposed chord-fractal pattern has a significant impact on IC capacitor, increasing the capacitance within a limited chip area. To reduce the device area, this paper presents a modified fractal algorithm. This proposed algorithm uses various initiators to perform chord iteration on the unit cell. The iteration procedure automatically generates an area-saving fractal layout of IC capacitor. To verify the proposed algorithm, an area-saving device of chord-fractal is fabricated using UMC 0.18-μm CMOS technology.