Design and Analysis of an Area-Efficient High Holding Voltage ESD Protection Device

Design and Analysis of an Area-Efficient High Holding Voltage ESD Protection Device

A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR) is proposed in this paper. With a distinguished feature of an imbedded floating P+ region, the GGISCR is demonstrated to be superior to the conventional low voltage trigge...

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Veröffentlicht in:IEEE transactions on electron devices 2015-02, Vol.62 (2), p.606-614
Hauptverfasser: Jie Zeng, Shurong Dong, Liou, Juin J., Yan Han, Lei Zhong, Weihuai Wang
Format: Artikel
Sprache:eng
Schlagworte:
Electrostatic discharges
Impact ionization
P-n junctions
Resistance
Robustness
Thyristors
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Zusammenfassung:A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR) is proposed in this paper. With a distinguished feature of an imbedded floating P+ region, the GGISCR is demonstrated to be superior to the conventional low voltage triggered SCR and GGnMOS in terms of high area efficiency and high holding voltage. The operational mechanism of GGISCR device is discussed in detail, and the effect of floating P+ region on the GGISCR's I-V characteristics is analyzed via TCAD simulation results as well.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2014.2381511