30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current

30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current

This paper presents the optimization of double-gate silicon (Si) tunnel field-effect transistors (TFETs). It shows that, for the heterodielectric structure, the I ON current is boosted by correctly positioning the source with respect to the gate edge. The second booster used in this paper is the Si...

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Veröffentlicht in:IEEE transactions on electron devices 2011-06, Vol.58 (6), p.1649-1654
Hauptverfasser: Anghel, C, Hraziia, Gupta, A, Amara, A, Vladimirescu, A
Format: Artikel
Sprache:eng
Schlagworte:
Ambipolar current
Applied sciences
Boosters
CMOS integrated circuits
Devices
Doping
Drains
Electronics
Exact sciences and technology
Gates
Logic gates
low- k spacer
Optimization
Performance evaluation
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon
Spacers
Transistors
tunnel field-effect transistor (TFET)
Tunneling
Tunnels (transportation)
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Beschreibung
Zusammenfassung:This paper presents the optimization of double-gate silicon (Si) tunnel field-effect transistors (TFETs). It shows that, for the heterodielectric structure, the I ON current is boosted by correctly positioning the source with respect to the gate edge. The second booster used in this paper is the Si thickness that is tuned in order to maximize the I ON current. The effects that lead to the performance increase are explained on a physical basis. We also demonstrate that the ambipolar character of the TFET is completely inhibited by using only one spacer of 30-nm length to separate the drain and the gate.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2011.2128320