Analysis of NMOS and PMOS Difference in V Variation With Large-Scale DMA-TEG

The mechanism of the V T variation difference between NMOS and PMOS is investigated. It is clarified that there is no correlation between V T and physical parameters such as gate length, gate width, gate oxide thickness, gate taper angle, sidewall width, channel strain, and gate poly-Si grain structure by integrated physical analysis (IPA). In IPA, the physical parameters of transistors with V T of -5sigma, median, and +5sigma are evaluated. It is also clarified that the variations of gate depletion and random charges at the gate oxide interface are not the dominant factors of V T variation, by electrical analyses using the Takeuchi plot. In these analyses, V T variations with varying process parameters are investigated. As a result of the analyses, only random channel dopant fluctuation (RDF) has a significant effect on V T variation. Since the simple RDF model alone cannot explain the V T variation difference between NMOS and PMOS, the channel boron clustering model is proposed as a possible mechanism of NMOS V T enhancement.