Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology

Conventional hardened cells are not robust enough to single event upset (SEU) in 28nm technology due to the scaling of the transistors. High soft error rate is caused by particle striking at cells and logic circuit in SRAM. This work proposes an SEU robust dual access 12T (DA-12T) SRAM with a radiation hardened crossbar-based peripheral circuit (CBPC). The proposed cell with 209% area penalty is more SEU robust than most cells. The CBPC can reduce the read failure rate of SRAMs. The new sense amplifier ensures the correct and rapid reading operation speed when suffering read disturbance. The experiment results show that the SEU cross-section of proposed cell is 60% of standard cell with dummy. Almost no read failure is observed in SRAM with CPBC when operational frequency exceeds 40MHz. Further investigation indicated that DA-12T cell and well isolation technique can reduce the read failure rate.