An Energy-Efficient Hierarchical Architecture for Time-Interleaved SAR ADC

An energy-efficient sampling architecture for time interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The architecture avoids the use of sampling buffers in order to minimize the number of noise sources on the input signal path and to reduce the power consumption on the track-and-hold (T&H) circuit. In addition, the noise optimization enables a size shrinking on the SAR ADC and, consequently, an extra power saving on the TI-ADC. This last optimization becomes particularly interesting in new CMOS technology nodes with high metal-capacitor matching. The tradeoffs of the typical hierarchical TI-ADC architecture are formulated and analyzed in comparison with this proposal. As an implementation example, an 8-bit 3.2-GS/s TI-ADC SAR is designed and fabricated in a 0.13- \mu \text{m} CMOS process. The implemented design uses four front sampling switches (phases), each one followed by eight asynchronous SAR ADCs. The design avoids all static current consumption across full input signal path up to digital output, pushing full TI-ADC efficiency to values similar to those achieved by the single SAR ADC unit. Measurements of the fabricated TI-ADC show 44.6-dB peak signal-to-noise-and-distortion ratio (7.12 effective number of bits) and 105-mW power consumption at 1.2 V.