An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled...

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Veröffentlicht in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2018-11, Vol.65 (11), p.3756-3768
Hauptverfasser: Kuo, Feng-Wei, Babaie, Masoud, Chen, Huan-Neng Ron, Cho, Lan-Chou, Jou, Chewn-Pu, Chen, Mark, Staszewski, Robert Bogdan
Format: Artikel
Sprache:eng
Schlagworte:
4G cellular
All-digital PLL (ADPLL)
Calibration
CMOS
Converters
Delays
digitally controlled oscillator (DCO)
Frequency modulation
Inverters
long-term evolution (LTE)
Phase locked loops
Radio frequency
spurs
time-to-digital converter (TDC)
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Zusammenfassung:We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2018.2855972