In-MRAM Computing Based on Complementary-Sensing Time-Based Readout Circuit Using Hybrid VGSOT-MTJ/GAA-CNTFET

Gate-all-around carbon nanotube field-effect-transistors (GAA-CNTFETs) and voltage-gated spin-orbit torque magnetic tunnel junctions (VGSOT-MTJs) are expected to realize significant savings in energy consumption and computing delay compared to the existing silicon-based FinFETs. This brief proposes...

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Veröffentlicht in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2024-09, p.1-1
Hauptverfasser: Tong, Zhongzhen, Sun, Sifan, Zhang, Kaili, Li, Chenghang, Zhou, Daming, Wang, Zhaohao, Lin, Xiaoyang, Zhao, Weisheng
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Sprache:eng
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Zusammenfassung:Gate-all-around carbon nanotube field-effect-transistors (GAA-CNTFETs) and voltage-gated spin-orbit torque magnetic tunnel junctions (VGSOT-MTJs) are expected to realize significant savings in energy consumption and computing delay compared to the existing silicon-based FinFETs. This brief proposes an in-MRAM computing macro based on a newly developed complementary-sensing time-based readout circuit (CSTRC) to accelerate binary neural networks (BNNs). An 8 kb MRAM was simulated using both GAA-CNTFET/VGSOT-MTJ and 14 nm FinFET/VGSOT-MTJ technologies to validate the effectiveness of the proposed design. The proposed CSTRC can achieve read operations and binary multiply-and-accumulate (BMAC) without additional peripheral circuits and achieve a notable decrease in the read bit error rate and column-level conditional row error rate by 1--5 and 1--13 orders of magnitude, respectively, compared to those reported previously. Moreover, under the GAA-CNTFET/VGSOT-MTJ process, the read energy consumption and delay were reduced by 59.1--78.9% and 23.9--29.7 %, respectively; the BMAC energy efficiency and throughput were 10231 1-b TOPS/W and 1.8 TOPS, respectively increased by 2.9 and 1.27 times at 0.8 V supply voltage when comparing to its 14-nm FinFET /VGSOT-MTJ counterparts.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2024.3460169