1.4-8 Gb/s Low Power Quarter-Rate Single-Loop Referenceless CDR With Unlimited Capture Range
This brief describes a low power quarter-rate single-loop clock and data recovery circuit (CDR) without a reference clock. A new frequency acquisition method is proposed, featuring unlimited frequency capture range and a short locking time. The proposed CDR has been designed and fabricated in a 28nm...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2024-09, Vol.71 (9), p.4061-4065 |
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| container_issue | 9 |
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| container_title | IEEE transactions on circuits and systems. II, Express briefs |
| container_volume | 71 |
| creator | Kim, Jin-Ho Kim, Tae Ho Lee, Hyung-Wook Park, Jeong-Mi Kang, Jin-Ku |
| description | This brief describes a low power quarter-rate single-loop clock and data recovery circuit (CDR) without a reference clock. A new frequency acquisition method is proposed, featuring unlimited frequency capture range and a short locking time. The proposed CDR has been designed and fabricated in a 28nm CMOS process, and measurement results show a capture range of 1.4Gb/s to 8Gb/s over the full voltage-controlled oscillator (VCO) operating range, with a locking time of approximately 1.37{\mu s} . The power efficiency is 0.71 [pJ/bit] at 8Gb/s input data. |
| doi_str_mv | 10.1109/TCSII.2024.3378302 |
| format | Article |
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A new frequency acquisition method is proposed, featuring unlimited frequency capture range and a short locking time. The proposed CDR has been designed and fabricated in a 28nm CMOS process, and measurement results show a capture range of 1.4Gb/s to 8Gb/s over the full voltage-controlled oscillator (VCO) operating range, with a locking time of approximately <inline-formula> <tex-math notation="LaTeX">1.37{\mu s} </tex-math></inline-formula>. The power efficiency is 0.71 [pJ/bit] at 8Gb/s input data.</description><identifier>ISSN: 1549-7747</identifier><identifier>EISSN: 1558-3791</identifier><identifier>DOI: 10.1109/TCSII.2024.3378302</identifier><identifier>CODEN: ITCSFK</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>CDR circuits ; Clock and data recovery (CDR) ; Clock recovery ; Clocks ; Data recovery ; Detectors ; Frequency measurement ; Locking ; low power CDR ; oversampling CDR power issue ; Periodic structures ; Power demand ; Power efficiency ; quarter rate CDR ; single-loop CDR ; Time-frequency analysis ; unlimited capture range ; Voltage controlled oscillators</subject><ispartof>IEEE transactions on circuits and systems. II, Express briefs, 2024-09, Vol.71 (9), p.4061-4065</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2024</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c247t-5060677055031bf2a331c32e25f38b1e613e15242d3dad66f8e137021610ff963</cites><orcidid>0009-0005-1462-5815 ; 0000-0002-3752-3740</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10474192$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27928,27929,54762</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10474192$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kim, Jin-Ho</creatorcontrib><creatorcontrib>Kim, Tae Ho</creatorcontrib><creatorcontrib>Lee, Hyung-Wook</creatorcontrib><creatorcontrib>Park, Jeong-Mi</creatorcontrib><creatorcontrib>Kang, Jin-Ku</creatorcontrib><title>1.4-8 Gb/s Low Power Quarter-Rate Single-Loop Referenceless CDR With Unlimited Capture Range</title><title>IEEE transactions on circuits and systems. II, Express briefs</title><addtitle>TCSII</addtitle><description>This brief describes a low power quarter-rate single-loop clock and data recovery circuit (CDR) without a reference clock. A new frequency acquisition method is proposed, featuring unlimited frequency capture range and a short locking time. The proposed CDR has been designed and fabricated in a 28nm CMOS process, and measurement results show a capture range of 1.4Gb/s to 8Gb/s over the full voltage-controlled oscillator (VCO) operating range, with a locking time of approximately <inline-formula> <tex-math notation="LaTeX">1.37{\mu s} </tex-math></inline-formula>. The power efficiency is 0.71 [pJ/bit] at 8Gb/s input data.</description><subject>CDR circuits</subject><subject>Clock and data recovery (CDR)</subject><subject>Clock recovery</subject><subject>Clocks</subject><subject>Data recovery</subject><subject>Detectors</subject><subject>Frequency measurement</subject><subject>Locking</subject><subject>low power CDR</subject><subject>oversampling CDR power issue</subject><subject>Periodic structures</subject><subject>Power demand</subject><subject>Power efficiency</subject><subject>quarter rate CDR</subject><subject>single-loop CDR</subject><subject>Time-frequency analysis</subject><subject>unlimited capture range</subject><subject>Voltage controlled oscillators</subject><issn>1549-7747</issn><issn>1558-3791</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkEFPg0AQhYnRxFr9A8bDJp6hOzu7LBwNam1CotI2XkwIhaHSUMBdSOO_t7U9eHpzeN-85HOcW-AeAA8ni2g-m3mCC-kh6gC5OHNGoFTgog7h_HDL0NVa6kvnytoN5yLkKEbOJ3jSDdh0NbEsbnfsrd2RYe9DZnoybpL1xOZVs67Jjdu2YwmVZKjJqSZrWfSYsI-q_2LLpq62VU8Fi7KuHwyxJGvWdO1clFlt6eaUY2f5_LSIXtz4dTqLHmI3F1L3ruI-97XmSnGEVSkyRMhRkFAlBisgH5BACSkKLLLC98uAADUX4AMvy9DHsXN__NuZ9nsg26ebdjDNfjJF4IAyVErsW-LYyk1rraEy7Uy1zcxPCjw9WEz_LKYHi-nJ4h66O0IVEf0DpJYQCvwFtJJqwg</recordid><startdate>20240901</startdate><enddate>20240901</enddate><creator>Kim, Jin-Ho</creator><creator>Kim, Tae Ho</creator><creator>Lee, Hyung-Wook</creator><creator>Park, Jeong-Mi</creator><creator>Kang, Jin-Ku</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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II, Express briefs</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kim, Jin-Ho</au><au>Kim, Tae Ho</au><au>Lee, Hyung-Wook</au><au>Park, Jeong-Mi</au><au>Kang, Jin-Ku</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>1.4-8 Gb/s Low Power Quarter-Rate Single-Loop Referenceless CDR With Unlimited Capture Range</atitle><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle><stitle>TCSII</stitle><date>2024-09-01</date><risdate>2024</risdate><volume>71</volume><issue>9</issue><spage>4061</spage><epage>4065</epage><pages>4061-4065</pages><issn>1549-7747</issn><eissn>1558-3791</eissn><coden>ITCSFK</coden><abstract>This brief describes a low power quarter-rate single-loop clock and data recovery circuit (CDR) without a reference clock. A new frequency acquisition method is proposed, featuring unlimited frequency capture range and a short locking time. The proposed CDR has been designed and fabricated in a 28nm CMOS process, and measurement results show a capture range of 1.4Gb/s to 8Gb/s over the full voltage-controlled oscillator (VCO) operating range, with a locking time of approximately <inline-formula> <tex-math notation="LaTeX">1.37{\mu s} </tex-math></inline-formula>. The power efficiency is 0.71 [pJ/bit] at 8Gb/s input data.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSII.2024.3378302</doi><tpages>5</tpages><orcidid>https://orcid.org/0009-0005-1462-5815</orcidid><orcidid>https://orcid.org/0000-0002-3752-3740</orcidid></addata></record> |
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| identifier | ISSN: 1549-7747 |
| ispartof | IEEE transactions on circuits and systems. II, Express briefs, 2024-09, Vol.71 (9), p.4061-4065 |
| issn | 1549-7747 1558-3791 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | CDR circuits Clock and data recovery (CDR) Clock recovery Clocks Data recovery Detectors Frequency measurement Locking low power CDR oversampling CDR power issue Periodic structures Power demand Power efficiency quarter rate CDR single-loop CDR Time-frequency analysis unlimited capture range Voltage controlled oscillators |
| title | 1.4-8 Gb/s Low Power Quarter-Rate Single-Loop Referenceless CDR With Unlimited Capture Range |
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