Ka-Band CMOS Power Amplifier Using Stacked Structure With Cascode-Like Operation

In this study, we proposed a Ka-band CMOS power amplifier (PA) using stacked structure with cascode-like operation to improve output power. The power stage of the PA consists of one common-source (CS) and two common-gate (CG) stages. The CS and the first CG stages were designed as stacked structure. In order to minimize the influence of parasitic inductance caused by the power transistor, an optimization method of the gate capacitor of the CG stage was proposed. In addition, in order to improve the output power and efficiency, the second CG stage was designed to operate close to the cascode operation through optimization of the gate capacitor of the second CG stage. To verify the feasibility of the proposed structure, we designed a Ka-band PA using a 65-nm RFCMOS process. At 29 GHz, the PA achieves P1dB of 22.4 dBm, saturation output power (PSAT) of 22.7 dBm, peak power-added efficiency (PAE) of 25.8%, and small signal gain of 25.2 dB, respectively. The PA is measured with 64-QAM signals, which has a 100-MHz channel bandwidth and a 9.7-dB PAPR. At 29 GHz, the PA achieves output power of 15.6 dBm with -25 dB EVM and the ACLR of -28.5 dBc, respectively.