A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation

A charge-domain compute-in-memory (CIM) macro is proposed to implement bit-scalable multiply-and-accumulate (MAC) operation with the cell-embedded digital-to-analog (DA) conversion and two-stage analog-to-digital (AD) conversion. The cell-embedded DA conversion is achieved among the capacitances inside the proposed 12T2C SRAM CIM cell, enabling 1-4 bit input. Then, multiple columns of CIM macro are merged to form 1/2/4 bit weight by controlling the switches in the multi-bit weight switch array. The proposed two-stage AD conversion circuit for 4-b output can reduce the output cycles with high energy efficiency. By using the CMOS 55nm design kit, the simulation results show that a 4kb CIM macro can achieve a throughput of 151.70-1260.31 GOPS and energy efficiency of 97.99-419.55 TOPS/W.