Low-Complexity Double-Node-Upset Resilient Latch Design Using Novel Stacked Cross-Coupled Elements

With aggressive scaling down in integrated circuit technology, the design of double-node-upset (DNU)-resilient latches have become a major issue regarding radiation hardening by design (RHBD). The conventional DNU-resilient latches are mostly based on the Muller C-element (MCE) and the dual-interloc...

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Veröffentlicht in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2023-09, Vol.70 (9), p.1-1
Hauptverfasser: Kang, Young-Min, Park, Jung-Jin, Kim, Geon-Hak, Chang, Ik-Joon, Kim, Jinsang
Format: Artikel
Sprache:eng
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Zusammenfassung:With aggressive scaling down in integrated circuit technology, the design of double-node-upset (DNU)-resilient latches have become a major issue regarding radiation hardening by design (RHBD). The conventional DNU-resilient latches are mostly based on the Muller C-element (MCE) and the dual-interlocked storage cell (DICE) element, which exhibit severe limitations: charge sharing during the read operation at a system level and large power consumption. Overcoming these limitations, this brief proposes a DNU-resilient latch based on a novel latch element. The proposed latch fully exploits upset polarity awareness, achieving the maximum number of single-event upset (SEU)-insensitive nodes. We develop a novel double modular redundancy architecture for the DNU-resilient latch design with one SEU-immune module. Based on simulation results, the proposed latch achieves up to 27.6X average power-delay-area-product (PDAP) improvement over state-of-the-art DNU-resilient latches.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2023.3266489