An Ising Model based Annealing Processor with 1024 Fully-Connected Spins for Combinatorial Optimization Problems

This brief presents a novel annealing processor (AP) design with 1024 fully-connected spins based on a modified Ising model annealing algorithm for combinatorial optimization problems. By adopting the proposed Turbo code-based interleaved random sequence generator (TCSG) and multi-spin update method, the memory usage is made considerable reduction and multi-spin parallel update is supported. The prototype is implemented using FPGA with the operation frequency of 100 MHz. We tested our design on various G-set problems with an average cut accuracy of 99.19% achieved. The proposed design outperforms the CPU-based method by achieving a max speedup of 1099×.