An Edge Neuromorphic Hardware with Fast On-Chip Error-Triggered Learning on Compressive Sensed Spikes

This brief proposes an edge neuromorphic hardware design for real-time energy-efficient applications. It is capable of fast on-chip learning on compressive sensed spikes utilizing an error-triggered learning mechanism. Our hardware architecture consists of two event-driven arrays of parallel computing cores, and adopts fine-grained pipeline circuits to boost processing speed. The architecture has good scalability and provides a flexible trade-off among processing speed, recognition accuracy and resource cost. Our design was prototyped on the very-low-cost Xilinx Zynq-7010 FPGA chip on a Zybo platform. The FPGA prototype realized a high processing speed of 4843 and 4931 frames/s with a high energy efficiency of 31.39 lJ/image and 30.83 lJ/image on the MNIST image set during training and inference, respectively. The prototype reached comparably high on-chip learning accuracies across a serial of datasets including both static images as well as spike event streams, e.g., 95.02% on the MNIST images and 84.46% on the N-MNIST streams.