An Impedance Adapting Compensation Scheme for High Current NMOS LDO Design

This brief presents a simple and power-efficient impedance adapting compensation scheme for high current NMOS low-dropout regulators (LDOs). By the proposed technique, the low-frequency node impedance retains to high value, while the high-frequency impedance is greatly attenuated. Therefore, both high gain and decent transient response is achieved simultaneously. Besides, the proposed impedance adaption waived the need for a commonly required power-hungry driver circuit, leading to a more simplified and energy-efficient design. In addition, the load-tracking technique is applied to further cancel the effect of load current variations, and helps achieve decent frequency and transient responses over a wide load range. Fabricated in a 0.35 {\mu }\text{m} CMOS process, the chip regulates an output voltage form 0.8 V to 1.8 V with 6 A current capacity and 114 mV maximum dropout voltage. The measurement results show an over-/undershoot voltages of 35.4 mV and −32.2 mV, respectively, for load transitions between 400 mA and 5A. The load and line regulations are 0.7mV/A and 0.12 mV/V, respectively, and the power supply rejections are −55 dB and −30 dB at 10 KHz and 1 MHz, respectively.