Estimating Thermal Noise in \Delta\Sigma ADCs Composed of Switched Capacitor Integrators

Thermal noise can be the limiting factor to achieving high resolution in ΔΣ modulator ADCs. Accurately estimating the impact of thermal noise on higher order modulator operation can be critical to predicting resolution. A mathematical model and simulation method for estimating the thermal noise in ΔΣ modulators composed of switched capacitor integrators have been developed and a new mechanism for thermal noise contribution from the integrator amplifier is presented. Compared with sampling noise, the integrator amplifier thermal noise can be a dominant noise source. An ADC experiment has been created to evaluate the accuracy of the noise estimation model. The experiment was implemented with a second order ΔΣ modulator ADC monitoring a low voltage input channel with a 250 kHz clock rate and 3 ms conversion time at an over sampling ratio of 768. The mathematical model predicts 14.7 stable bits of resolution, the simulation method predicts 14.7 bits of resolution, and the hardware was measured to have 14.6 bits of resolution at the 3 ms conversion rate.