A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM

This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13-μm CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed technique, the maximum speed is 2 Gb/s/ch, which is increased by more than 120% under the same channel condition. The power consumption is also reduced compared to that of the conventional scheme; the energy efficiency is 104 fJ/b/mm, respectively.