Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry

Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry

In this brief, we show that by exploiting the inherent symmetry of the discrete wavelet transform (DWT) algorithm and consequently storing only the nonrepetitive combinations of filter coefficients, the size of required memory can be significantly reduced. Subsequently, a memory-efficient architectu...

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Veröffentlicht in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2009-04, Vol.56 (4), p.285-289
Hauptverfasser: Acharyya, A., Maharatna, K., Al-Hashimi, B.M., Gunn, S.R.
Format: Artikel
Sprache:eng
Schlagworte:
Algorithms
Arithmetic
Circuits
Computer architecture
Consumption
Discrete Wavelet Transform
Discrete wavelet transforms
Distributed arithmetic (DA)
Energy consumption
Filters
Gunn devices
Hardware
Inverse
low-power architecture
multiplierless implementation
Signal processing
Signal processing algorithms
Silicon
Symmetry
very large scale integration
wavelet
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Beschreibung
Zusammenfassung:In this brief, we show that by exploiting the inherent symmetry of the discrete wavelet transform (DWT) algorithm and consequently storing only the nonrepetitive combinations of filter coefficients, the size of required memory can be significantly reduced. Subsequently, a memory-efficient architecture for DWT/inverse DWT is proposed. It occupies 6.5-mm 2 silicon area and consumes 46.8-muW power at 1 MHz for 1.2 V using 0.13-mum standard cell technology.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2009.2015386