A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits
A transient electrothermal simulation of a 3-D integrated circuit (3DIC) is reported that uses dynamic modeling of the thermal network and hierarchical electrothermal simulation. This is a practical alternative to full transistor electrothermal simulations that are computationally prohibitive. Simul...
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Veröffentlicht in: | IEEE transactions on components, packaging, and manufacturing technology (2011) packaging, and manufacturing technology (2011), 2012-04, Vol.2 (4), p.660-667 |
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Hauptverfasser: | , , , , , , , , , |
Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | A transient electrothermal simulation of a 3-D integrated circuit (3DIC) is reported that uses dynamic modeling of the thermal network and hierarchical electrothermal simulation. This is a practical alternative to full transistor electrothermal simulations that are computationally prohibitive. Simulations are compared to measurements for a token-generating asynchronous 3DIC clocking at a maximum frequency of 1 GHz. The electrical network is based on computationally efficient electrothermal macromodels of standard and custom cells. These are linked in a physically consistent manner with a detailed thermal network extracted from an OpenAccess layout file. Coupled with model-order reduction techniques, hierarchical dynamic electrothermal simulation of large 3DICs is shown to be tractable, yielding spatial and temporal selected transistor-level thermal profiles. |
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ISSN: | 2156-3950 2156-3985 |
DOI: | 10.1109/TCPMT.2011.2178414 |