A High-Speed Sequential Decoder: Prototype Design and Test

A High-Speed Sequential Decoder: Prototype Design and Test

We describe the design of a rate-1/2 hard-decision sequential decoder capable of operation at data rates up to 5 M bit/s. Test results are given for digitally generated errors, white noise, and real channels. The results are substantially in agreement with predictions of a coding gain of the order o...

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Veröffentlicht in:IEEE transactions on communication technology 1971-10, Vol.19 (5), p.821-835
Hauptverfasser: Forney, G., Bower, E.
Format: Artikel
Sprache:eng
Schlagworte:
Clocks
Communications technology
Costs
Decoding
Hardware
Laboratories
Prototypes
Sequential analysis
Testing
White noise
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Beschreibung
Zusammenfassung:We describe the design of a rate-1/2 hard-decision sequential decoder capable of operation at data rates up to 5 M bit/s. Test results are given for digitally generated errors, white noise, and real channels. The results are substantially in agreement with predictions of a coding gain of the order of 5 dB at a 10 -5 error rate.
ISSN:0018-9332
2162-2175
DOI:10.1109/TCOM.1971.1090721