A fast-acquisition PLL using split half-duty sampled feedforward loop filter

A fast-acquisition PLL using split half-duty sampled feedforward loop filter

We reduce the pattern jitter and acquisition time of a phase-locked loop (PLL) by adopting the split half-duty sampled feedforward loop filter. A prototype designed and fabricated in a 0.18μm standard CMOS technology has a 40% lower acquisition time than a PLL without operating in fast acquisition m...

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Veröffentlicht in:IEEE transactions on consumer electronics 2010-08, Vol.56 (3), p.1856-1859
Hauptverfasser: Shin, Woo-yeol, Kim, Manho, Hong, Gi-moon, Kim, Suhwan
Format: Artikel
Sprache:eng
Schlagworte:
Acquisition time
Acquisitions
Capacitance
Capacitors
Charge pumps
CMOS
Electrical engineering
Electronics
Feedforward
Feedforward neural networks
Jitter
loop filter
Marketing
pattern jitter
phase locked loop (PLL)
Phase locked loops
Reinforced concrete
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Beschreibung
Zusammenfassung:We reduce the pattern jitter and acquisition time of a phase-locked loop (PLL) by adopting the split half-duty sampled feedforward loop filter. A prototype designed and fabricated in a 0.18μm standard CMOS technology has a 40% lower acquisition time than a PLL without operating in fast acquisition mode. Its peak-to-peak jitter is 26% less than that of a PLL with a conventional 2nd-order RC loop filter.
ISSN:0098-3063
1558-4127
DOI:10.1109/TCE.2010.5606337