A Parametric EDA Method for Coplanar Waveguide Channel Recognition and Air-Bridge Construction in Quantum Chip Design

Coplanar waveguides (CPWs) are ideally suited for coherently interfacing resonators with superconducting qubits. However, integrating CPWs with circuit elements on quantum chips involves curvature and discontinuities of the central conductors and corresponding ground planes, which may generate undesired parasitic modes. Experiments have demonstrated that air-bridges can effectively suppress this unwanted effect. Nevertheless, as quantum processors increase in size, manual air-bridge placement on the chip layout becomes increasingly time-consuming and error-prone. Automation of this process is therefore highly desirable, especially when the center line (channel) of the CPWs is not pre-established. In this article, we propose a parametric EDA method for CPW channel identification and air-bridge construction in quantum chips. Our approach applies to both separated and full-package air-bridges and scales efficiently, with running time linear in the number of points and quadratic in the number of arcs in the corresponding chip layout. We evaluate our approach on a set of open-source quantum chip layouts, generating air-bridges in times ranging from 0.05 to 0.5 s-a practical speedup of over 10000 times compared to manual generation. Furthermore, We propose two original quantitative metrics, accuracy and overlap, and verify that our method yields reliable results, producing air-bridges in the required shapes and locations. We fabricate a 13-qubit chip using our method for air-bridge placement and observe excellent performance with minimal microwave and flux crosstalk. This research enables rapid generation of air-bridges when CPW channels are not prespecified, paving the way for more flexible, automated, and modular design of superconducting quantum EDA.