ATPG for Delay Defects in Current Mode Threshold Logic Circuits

ATPG for Delay Defects in Current Mode Threshold Logic Circuits

An automatic test pattern generation approach to detect delay defects in a circuit consisting of current mode threshold logic gates is introduced. Each generated pattern should excite the maximum propagation delay at the fault site. Manufactured weights may vary, and maximum delay is ensured by appl...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems 2016-11, Vol.35 (11), p.1903-1913
Hauptverfasser: Palaniswamy, Ashok Kumar, Tragoudas, Spyros, Haniotakis, Themistoklis
Format: Artikel
Sprache:eng
Schlagworte:
Automatic test pattern generation
Automatic test pattern generation (ATPG)
binary decision diagram (BDD)
Boolean functions
Circuit faults
Circuits
Data structures
Defects
Delay
delay testing
Delays
Design engineering
Efficiency
Faults
Logic gates
Mathematical model
Test pattern generators
Threshold logic
threshold logic gate (TLG)
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Beschreibung
Zusammenfassung:An automatic test pattern generation approach to detect delay defects in a circuit consisting of current mode threshold logic gates is introduced. Each generated pattern should excite the maximum propagation delay at the fault site. Manufactured weights may vary, and maximum delay is ensured by applying an appropriately generated set of patterns per fault. Experimental results show the efficiency of the proposed methods.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2016.2533863