Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs

This paper presents the first multiobjective microarchitectural floorplanning algorithm for high-performance processors implemented in two-dimensional (2-D) and three-dimensional (3-D) ICs. The floorplanner takes a microarchitectural netlist and determines the dimension as well as the placement of t...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2007-01, Vol.26 (1), p.38-52
Hauptverfasser:	Healy, M., Vittes, M., Ekpanyapong, M., Ballapuram, C.S., Sung Kyu Lim, Lee, H.-H.S., Loh, G.H.
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Bonding Clocks Computer aided design Delay Design engineering Linear programming Microarchitectural floorplanning Microarchitecture Optimization Partitioning Partitioning algorithms performance optimization Processors Semiconductor device packaging Simulated annealing thermal distribution Three-dimensional integrated circuits three-dimensional integrated circuits (3-D ICs) Two dimensional displays Wire
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