A Procedure for Placement of Standard-Cell VLSI Circuits

This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 1985-01, Vol.4 (1), p.92-98
Hauptverfasser:	Dunlop, A.E., Kernighan, B.W.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Circuits and Systems Society Computer industry Computer networks Computer science Design automation Design methodology Electronics Exact sciences and technology Integrated circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Time of arrival estimation Very large scale integration
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Beschreibung
Zusammenfassung:	This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting for external connections at each level of partitioning. The placement procedure is in production use as part of an automated design system; it has been used in the design of more than 40 chips, in CMOS, NMOS, and bipolar technologies.
ISSN:	0278-0070 1937-4151
DOI:	10.1109/TCAD.1985.1270101