Power Hardware-in-the-Loop Testing of an Air Coil Superconducting Fault Current Limiter Demonstrator

This paper discusses power hardware-in-the-loop (PHIL) tests performed at the Center for Advanced Power Systems (CAPS) with a 60-kVA, 400-V, z= 6% air coil (AC) superconducting fault current limiter (AC-SFCL) demonstrator. The demonstrator was designed, built, and successfully tested for fault current limitation at Karlsruhe Institute of Technology (KIT) . Initial PHIL testing at CAPS focused on a single-phase setup to verify the results obtained at KIT. Subsequent PHIL testing in a three-phase system was accomplished by interfacing the physical AC-SFCL to the simulated system in phase A and simulating the effect of AC-SFCL devices in the other two phases. This was done by estimating the resistance and inductance of the AC-SFCL through instantaneous voltage and current measurements and inserting this impedance in phases B and C for cases in which these phases were part of the short-circuit path. For these PHIL experiments, the modified damping impedance (DIM) interface algorithm was employed. It was possible to reproduce earlier reference measurements using the modified DIM PHIL interface algorithm. The PHIL system was then used to create a three-phase power system consisting of a generator, a load, and a short-circuit path. Symmetrical and unsymmetrical short circuits have been performed with and without ground connection. The PHIL system maintained stability throughout the experiments, and the results show suitable current limitation for all performed types of short circuits.