Return Path Assumption Validation for Inductance Modeling in Digital Design

Inductance modeling for on-chip interconnects in a typical digital environment is proposed. Regarding the effective loop inductance computation, the issue of current return path assumptions is first discussed. Then, sensible assumptions about the return path localization are presented and systematic...

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Veröffentlicht in:	IEEE transactions on advanced packaging 2007-05, Vol.30 (2), p.295-300
Hauptverfasser:	David, L., Cregut, C., Huret, F., Quere, Y., Nyer, F.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Circuit noise Circuit properties Computation Coupling circuits Delay effects Delay estimation Design engineering Design. Technologies. Operation analysis. Testing Digital Digital circuit Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Engineering Sciences Exact sciences and technology Frequency Inductance Integrated circuit interconnections Integrated circuits interconnection Localization Mathematical models Micro and nanotechnologies Microelectronics modeling Packaging Position (location) Propagation delay RLC circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Working environment noise
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Beschreibung
Zusammenfassung:	Inductance modeling for on-chip interconnects in a typical digital environment is proposed. Regarding the effective loop inductance computation, the issue of current return path assumptions is first discussed. Then, sensible assumptions about the return path localization are presented and systematically validated. Finally, representative structure models allowing prelayout effective inductance estimations are suggested.
ISSN:	1521-3323 1557-9980
DOI:	10.1109/TADVP.2007.896002