Energy-Efficient Parallel Interconnects for Chiplet Integration

Energy-Efficient Parallel Interconnects for Chiplet Integration

Integrating multiple chiplets in advanced packaging requires high-bandwidth and energy-efficient chiplet-to-chiplet interconnects. Parallel interconnects have emerged as the preferred interface for chiplet integration. This paper provides an overview of the physical layer design of the Advanced Inte...

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Veröffentlicht in:IEEE MICRO 2024-08, p.1-8
Hauptverfasser: Tang, Wei, Liu, Chester, Zhang, Zhengya
Format: Artikel
Sprache:eng
Schlagworte:
Bandwidth
Chiplets
Clocks
Electrostatic discharges
Energy efficiency
Tuning
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Liu, Chester
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description Integrating multiple chiplets in advanced packaging requires high-bandwidth and energy-efficient chiplet-to-chiplet interconnects. Parallel interconnects have emerged as the preferred interface for chiplet integration. This paper provides an overview of the physical layer design of the Advanced Interface Bus (AIB), highlighting its simplicity and high energy efficiency. Additionally, we present a concrete example of successful chiplet integration employing AIB.
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fullrecord <record><control><sourceid>crossref_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_MM_2024_3450841</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10659059</ieee_id><sourcerecordid>10_1109_MM_2024_3450841</sourcerecordid><originalsourceid>FETCH-LOGICAL-c619-2d21d6cecb86915e93c73561db0398b7d16e2e58e56ea8394af692f1b6f92bd73</originalsourceid><addsrcrecordid>eNpNj7FOwzAURS0EEqEwszDkB5z62bEdTwhFpVRqBEN3y3GeS1BIKjtL_x5KOzDd4d5zpUPII7ACgJll0xSc8bIQpWRVCVckAyM0LaEU1yRjXHMKWvBbcpfSF2NMclZl5Hk1Ytwf6SqE3vc4zvmHi24YcMg344zRT-OIfk55mGJef_aHAee_Zh_d3E_jPbkJbkj4cMkF2b2udvUb3b6vN_XLlnoFhvKOQ6c8-rZSBiQa4bWQCrqWCVO1ugOFHGWFUqGrhCldUIYHaFUwvO20WJDl-dbHKaWIwR5i_-3i0QKzJ33bNPakby_6v8TTmegR8d9aScOkET-aplZI</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Energy-Efficient Parallel Interconnects for Chiplet Integration</title><source>IEEE Electronic Library (IEL)</source><creator>Tang, Wei ; Liu, Chester ; Zhang, Zhengya</creator><creatorcontrib>Tang, Wei ; Liu, Chester ; Zhang, Zhengya</creatorcontrib><description>Integrating multiple chiplets in advanced packaging requires high-bandwidth and energy-efficient chiplet-to-chiplet interconnects. Parallel interconnects have emerged as the preferred interface for chiplet integration. This paper provides an overview of the physical layer design of the Advanced Interface Bus (AIB), highlighting its simplicity and high energy efficiency. Additionally, we present a concrete example of successful chiplet integration employing AIB.</description><identifier>ISSN: 0272-1732</identifier><identifier>EISSN: 1937-4143</identifier><identifier>DOI: 10.1109/MM.2024.3450841</identifier><identifier>CODEN: IEMIDZ</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bandwidth ; Chiplets ; Clocks ; Electrostatic discharges ; Energy efficiency ; Tuning</subject><ispartof>IEEE MICRO, 2024-08, p.1-8</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10659059$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54737</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10659059$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Tang, Wei</creatorcontrib><creatorcontrib>Liu, Chester</creatorcontrib><creatorcontrib>Zhang, Zhengya</creatorcontrib><title>Energy-Efficient Parallel Interconnects for Chiplet Integration</title><title>IEEE MICRO</title><addtitle>MM</addtitle><description>Integrating multiple chiplets in advanced packaging requires high-bandwidth and energy-efficient chiplet-to-chiplet interconnects. Parallel interconnects have emerged as the preferred interface for chiplet integration. This paper provides an overview of the physical layer design of the Advanced Interface Bus (AIB), highlighting its simplicity and high energy efficiency. Additionally, we present a concrete example of successful chiplet integration employing AIB.</description><subject>Bandwidth</subject><subject>Chiplets</subject><subject>Clocks</subject><subject>Electrostatic discharges</subject><subject>Energy efficiency</subject><subject>Tuning</subject><issn>0272-1732</issn><issn>1937-4143</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNj7FOwzAURS0EEqEwszDkB5z62bEdTwhFpVRqBEN3y3GeS1BIKjtL_x5KOzDd4d5zpUPII7ACgJll0xSc8bIQpWRVCVckAyM0LaEU1yRjXHMKWvBbcpfSF2NMclZl5Hk1Ytwf6SqE3vc4zvmHi24YcMg344zRT-OIfk55mGJef_aHAee_Zh_d3E_jPbkJbkj4cMkF2b2udvUb3b6vN_XLlnoFhvKOQ6c8-rZSBiQa4bWQCrqWCVO1ugOFHGWFUqGrhCldUIYHaFUwvO20WJDl-dbHKaWIwR5i_-3i0QKzJ33bNPakby_6v8TTmegR8d9aScOkET-aplZI</recordid><startdate>20240828</startdate><enddate>20240828</enddate><creator>Tang, Wei</creator><creator>Liu, Chester</creator><creator>Zhang, Zhengya</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20240828</creationdate><title>Energy-Efficient Parallel Interconnects for Chiplet Integration</title><author>Tang, Wei ; Liu, Chester ; Zhang, Zhengya</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c619-2d21d6cecb86915e93c73561db0398b7d16e2e58e56ea8394af692f1b6f92bd73</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Bandwidth</topic><topic>Chiplets</topic><topic>Clocks</topic><topic>Electrostatic discharges</topic><topic>Energy efficiency</topic><topic>Tuning</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Tang, Wei</creatorcontrib><creatorcontrib>Liu, Chester</creatorcontrib><creatorcontrib>Zhang, Zhengya</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE MICRO</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tang, Wei</au><au>Liu, Chester</au><au>Zhang, Zhengya</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Energy-Efficient Parallel Interconnects for Chiplet Integration</atitle><jtitle>IEEE MICRO</jtitle><stitle>MM</stitle><date>2024-08-28</date><risdate>2024</risdate><spage>1</spage><epage>8</epage><pages>1-8</pages><issn>0272-1732</issn><eissn>1937-4143</eissn><coden>IEMIDZ</coden><abstract>Integrating multiple chiplets in advanced packaging requires high-bandwidth and energy-efficient chiplet-to-chiplet interconnects. Parallel interconnects have emerged as the preferred interface for chiplet integration. This paper provides an overview of the physical layer design of the Advanced Interface Bus (AIB), highlighting its simplicity and high energy efficiency. Additionally, we present a concrete example of successful chiplet integration employing AIB.</abstract><pub>IEEE</pub><doi>10.1109/MM.2024.3450841</doi><tpages>8</tpages></addata></record>
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subjects Bandwidth
Chiplets
Clocks
Electrostatic discharges
Energy efficiency
Tuning
title Energy-Efficient Parallel Interconnects for Chiplet Integration
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-22T08%3A43%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Energy-Efficient%20Parallel%20Interconnects%20for%20Chiplet%20Integration&rft.jtitle=IEEE%20MICRO&rft.au=Tang,%20Wei&rft.date=2024-08-28&rft.spage=1&rft.epage=8&rft.pages=1-8&rft.issn=0272-1732&rft.eissn=1937-4143&rft.coden=IEMIDZ&rft_id=info:doi/10.1109/MM.2024.3450841&rft_dat=%3Ccrossref_RIE%3E10_1109_MM_2024_3450841%3C/crossref_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=10659059&rfr_iscdi=true