Energy-Efficient Parallel Interconnects for Chiplet Integration

Integrating multiple chiplets in advanced packaging requires high-bandwidth and energy-efficient chiplet-to-chiplet interconnects. Parallel interconnects have emerged as the preferred interface for chiplet integration. This paper provides an overview of the physical layer design of the Advanced Interface Bus (AIB), highlighting its simplicity and high energy efficiency. Additionally, we present a concrete example of successful chiplet integration employing AIB.