Co-Design of Inter-Chiplet, Package, and System Interconnect Protocols

Co-Design of Inter-Chiplet, Package, and System Interconnect Protocols

AI applications are adopting modular tile design paradigms for compute and networking chiplets. The integration of UCIe as a die-to-die interconnect for low latency and power savings allows a disaggregation of large monolithic dies. This paper covers inter-chiplet architectures that can be built tow...

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Veröffentlicht in:IEEE MICRO 2024-08, p.1-4
Hauptverfasser: Carusone, Tony Chan, Dunwell, Dustin, Gupta, Sundeep, Giuliano, Letizia, Auge, Adrien, Klempa, Michael, Fung, Sue Hung
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Bandwidth
Chiplets
Computer architecture
Crosstalk
Packaging
Routing
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container_title IEEE MICRO
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creator Carusone, Tony Chan
Dunwell, Dustin
Gupta, Sundeep
Giuliano, Letizia
Auge, Adrien
Klempa, Michael
Fung, Sue Hung
description AI applications are adopting modular tile design paradigms for compute and networking chiplets. The integration of UCIe as a die-to-die interconnect for low latency and power savings allows a disaggregation of large monolithic dies. This paper covers inter-chiplet architectures that can be built towards a chiplet portfolio for escalating bandwidth needs in networking and AI/ML. The electrical layer of UCIe design verification is illustrated. In addition, the topic of package design and challenges associated with the integration of the PHY, in both standard and advanced packaging, are discussed.
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subjects Bandwidth
Chiplets
Computer architecture
Crosstalk
Packaging
Routing
title Co-Design of Inter-Chiplet, Package, and System Interconnect Protocols
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