Co-Design of Inter-Chiplet, Package, and System Interconnect Protocols

AI applications are adopting modular tile design paradigms for compute and networking chiplets. The integration of UCIe as a die-to-die interconnect for low latency and power savings allows a disaggregation of large monolithic dies. This paper covers inter-chiplet architectures that can be built towards a chiplet portfolio for escalating bandwidth needs in networking and AI/ML. The electrical layer of UCIe design verification is illustrated. In addition, the topic of package design and challenges associated with the integration of the PHY, in both standard and advanced packaging, are discussed.