FabScalar: Automating Superscalar Core Design
Providing multiple superscalar core types on a chip, each tailored to different classes of instruction-level behavior, is an exciting direction for increasing processor performance and energy efficiency. Unfortunately, processor design and verification effort increases with each additional core type...
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| Veröffentlicht in: | IEEE MICRO 2012-05, Vol.32 (3), p.48-59 |
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| container_end_page | 59 |
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| container_issue | 3 |
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| container_title | IEEE MICRO |
| container_volume | 32 |
| creator | Choudhary, Niket K. Wadhavkar, Salil V. Shah, Tanmay A. Mayukh, Hiran Gandhi, Jayneel Dwiel, Brandon H. Navada, Sandeep Najaf-abadi, Hashem H. Rotenberg, Eric |
| description | Providing multiple superscalar core types on a chip, each tailored to different classes of instruction-level behavior, is an exciting direction for increasing processor performance and energy efficiency. Unfortunately, processor design and verification effort increases with each additional core type, limiting the microarchitectural diversity that can be practically implemented. FabScalar aims to automate superscalar core design, opening up processor design to microarchitectural diversity and its many opportunities. |
| doi_str_mv | 10.1109/MM.2012.23 |
| format | Article |
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| identifier | ISSN: 0272-1732 |
| ispartof | IEEE MICRO, 2012-05, Vol.32 (3), p.48-59 |
| issn | 0272-1732 1937-4143 |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_MM_2012_23 |
| source | IEEE Electronic Library (IEL) |
| subjects | Automation Chips Computer architecture Constraining design automation Energy efficiency Excitation Hardware design languages heterogeneous (asymmetric) multicore ILP Instruction sets instruction-level parallelism Microarchitecture Microprocessors Multicore processing Program processors specialization superscalar processors |
| title | FabScalar: Automating Superscalar Core Design |
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