FabScalar: Automating Superscalar Core Design

Providing multiple superscalar core types on a chip, each tailored to different classes of instruction-level behavior, is an exciting direction for increasing processor performance and energy efficiency. Unfortunately, processor design and verification effort increases with each additional core type...

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Veröffentlicht in:	IEEE MICRO 2012-05, Vol.32 (3), p.48-59
Hauptverfasser:	Choudhary, Niket K., Wadhavkar, Salil V., Shah, Tanmay A., Mayukh, Hiran, Gandhi, Jayneel, Dwiel, Brandon H., Navada, Sandeep, Najaf-abadi, Hashem H., Rotenberg, Eric
Format:	Artikel
Sprache:	eng
Schlagworte:	Automation Chips Computer architecture Constraining design automation Energy efficiency Excitation Hardware design languages heterogeneous (asymmetric) multicore ILP Instruction sets instruction-level parallelism Microarchitecture Microprocessors Multicore processing Program processors specialization superscalar processors
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Beschreibung
Zusammenfassung:	Providing multiple superscalar core types on a chip, each tailored to different classes of instruction-level behavior, is an exciting direction for increasing processor performance and energy efficiency. Unfortunately, processor design and verification effort increases with each additional core type, limiting the microarchitectural diversity that can be practically implemented. FabScalar aims to automate superscalar core design, opening up processor design to microarchitectural diversity and its many opportunities.
ISSN:	0272-1732 1937-4143
DOI:	10.1109/MM.2012.23