Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures

Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures

The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-opti...

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Veröffentlicht in:IEEE MICRO 2010-01, Vol.30 (1), p.29-29
Hauptverfasser: Hardavellas, N., Ferdman, M., Falsafi, B., Ailamaki, A.
Format: Artikel
Sprache:eng
Schlagworte:
Aggregates
Architecture
Blocking
Cache
cache memories
Classification
Communication switching
Computer architecture
Cooling
Costs
Counting
data placement
Delay effects
Manufacturing processes
Microprocessors
multicore
Nonuniform
nonuniform cache architectures
On-line systems
parallel architectures
Placement
Placing
Robustness
Switches
Wire
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Beschreibung
Zusammenfassung:The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-optimal cache block placement by classifying blocks online and placing data close to the cores that use them.
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2010.22