Leveraging Wire Properties at the Microarchitecture Level

Leveraging Wire Properties at the Microarchitecture Level

In future microprocessors, communication will emerge as a major bottleneck. The authors advocate composing future interconnects of some wires that minimize latency, some that maximize bandwidth, and some that minimize power. A microarchitecture aware of these wire characteristics can steer on-chip d...

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Veröffentlicht in:IEEE MICRO 2006-11, Vol.26 (6), p.40-52
Hauptverfasser: Balasubramonian, R., Muralimanohar, N., Ramani, K., Liqun Cheng, Carter, J.B.
Format: Artikel
Sprache:eng
Schlagworte:
advanced technologies
Bandwidth
Composing
Costs
Data transfer (computers)
Data transmission
Delay
Design engineering
Energy conservation
energy-aware systems
Integrated circuit interconnections
interconnection architectures
interconnections
interprocessor communications
Microarchitecture
Microprocessor chips
Microprocessors
multiprocessor systems
Optical interconnections
Optical sensors
Optical transmitters
Performance enhancement
Power transmission lines
Wire
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Beschreibung
Zusammenfassung:In future microprocessors, communication will emerge as a major bottleneck. The authors advocate composing future interconnects of some wires that minimize latency, some that maximize bandwidth, and some that minimize power. A microarchitecture aware of these wire characteristics can steer on-chip data transfers to the most appropriate wires, thus improving performance and saving energy
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2006.123