Low-Power, Resilient Interconnection with Orthogonal Latin Squares
A reliable, energy-efficient on-chip interconnection network employing low-swing signaling can be designed by incorporating error-correcting code. Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, while also lowering energy consumption. When applied to a 6...
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| Veröffentlicht in: | IEEE design & test of computers 2011-03, Vol.28 (2), p.30-39 |
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| container_title | IEEE design & test of computers |
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| creator | Seung Eun Lee Yoon Seok Yang Choi, G S Wei Wu Iyer, R |
| description | A reliable, energy-efficient on-chip interconnection network employing low-swing signaling can be designed by incorporating error-correcting code. Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, while also lowering energy consumption. When applied to a 64-bit link using a 45-nm CMOS technology with low-swing signaling, OLSC provided up to 55% energy reduction, with only a small area overhead and no loss in reliability. |
| doi_str_mv | 10.1109/MDT.2011.35 |
| format | Article |
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| source | IEEE Electronic Library (IEL) |
| subjects | CMOS Crosstalk Decoding design and test ECC Encoding Energy consumption Energy use Error correction codes error-correcting code Errors Interconnection IP networks Links Networks OFDM OLSC on-chip interconnection orthogonal Latin square Reduction resilience and low power design System-on-a-chip |
| title | Low-Power, Resilient Interconnection with Orthogonal Latin Squares |
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