Physical Techniques for Chip-Backside IC Debug in Nanotechnologies

Physical failure analysis remains indispensable for final defect confirmation, but is increasingly difficult due to semiconductor technology advances with smaller feature sizes, many metal layers, and flip-chip packaging. This article reports on how, despite an uphill battle, constant innovations ke...

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Veröffentlicht in:	IEEE design & test of computers 2008-05, Vol.25 (3), p.250-257
Hauptverfasser:	Boit, C., Schlangen, R., Kerst, U., Lundquist, T.
Format:	Artikel
Sprache:	eng
Schlagworte:	backside Circuits debug Design engineering electron beam probing Failure analysis Functional analysis Integrated circuits Laser theory laser voltage probing Milling Nanocomposites Nanomaterials nanoscale Nanoscale devices Nanostructure optical probing Packaging Particle beams photoelectric laser stimulation Photonic band gap Semiconductors Silicon on insulator technology thermal laser stimulation time-resolved emission Voltage
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Beschreibung
Zusammenfassung:	Physical failure analysis remains indispensable for final defect confirmation, but is increasingly difficult due to semiconductor technology advances with smaller feature sizes, many metal layers, and flip-chip packaging. This article reports on how, despite an uphill battle, constant innovations keep physical failure analysis going.
ISSN:	0740-7475 2168-2356 1558-1918 2168-2364
DOI:	10.1109/MDT.2008.82