Scan Design Using Standard Flip-Flops
Classical scan designs require properly augmented flip-flops, often called scan flip-flops. Problems stem from the high area overhead implied by the need for these flip-flops or the inability to modify standard flip-flops. The authors outline a method to design easily testable sequential circuits th...
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Veröffentlicht in: | IEEE design & test of computers 1987-02, Vol.4 (1), p.52-54 |
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container_title | IEEE design & test of computers |
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creator | Reddy, Sudhakar M. Dandapani, R. |
description | Classical scan designs require properly augmented flip-flops, often called scan flip-flops. Problems stem from the high area overhead implied by the need for these flip-flops or the inability to modify standard flip-flops. The authors outline a method to design easily testable sequential circuits that achieve scan designs using standard (unmodified) flip-flops. |
doi_str_mv | 10.1109/MDT.1987.295115 |
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fullrecord | <record><control><sourceid>crossref_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_MDT_1987_295115</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4069934</ieee_id><sourcerecordid>10_1109_MDT_1987_295115</sourcerecordid><originalsourceid>FETCH-LOGICAL-c259t-28d38a1b8b717bed8649b836c8b436f9affc9b676e5ac085326abeea18d31fdd3</originalsourceid><addsrcrecordid>eNo9zztPwzAUhmELgUQozAwsWRid-sT3EbUEkIoY2s6Wr1VQSKO4C_-eVKmYznLeT3oQegRSARC9_FzvKtBKVrXmAPwKFcC5wqBBXaOCSEawZJLforucvwkhAEIU6HnrbV-uY24PfbnPbX8otyfbBzuGsunaATfdccj36CbZLseHy12gffO6W73jzdfbx-plg33N9QnXKlBlwSknQboYlGDaKSq8coyKpG1KXjshReTWE8VpLayL0cLUQQqBLtBy3vXjMecxJjOM7Y8dfw0Qc1aaSWnOSjMrp-JpLtoY4_83I0JryugfZnJM-w</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Scan Design Using Standard Flip-Flops</title><source>IEEE/IET Electronic Library (IEL)</source><creator>Reddy, Sudhakar M. ; Dandapani, R.</creator><creatorcontrib>Reddy, Sudhakar M. ; Dandapani, R.</creatorcontrib><description>Classical scan designs require properly augmented flip-flops, often called scan flip-flops. Problems stem from the high area overhead implied by the need for these flip-flops or the inability to modify standard flip-flops. The authors outline a method to design easily testable sequential circuits that achieve scan designs using standard (unmodified) flip-flops.</description><identifier>ISSN: 0740-7475</identifier><identifier>EISSN: 1558-1918</identifier><identifier>DOI: 10.1109/MDT.1987.295115</identifier><identifier>CODEN: IDTCEC</identifier><language>eng</language><publisher>IEEE Computer Society</publisher><ispartof>IEEE design & test of computers, 1987-02, Vol.4 (1), p.52-54</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c259t-28d38a1b8b717bed8649b836c8b436f9affc9b676e5ac085326abeea18d31fdd3</citedby><cites>FETCH-LOGICAL-c259t-28d38a1b8b717bed8649b836c8b436f9affc9b676e5ac085326abeea18d31fdd3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4069934$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4069934$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Reddy, Sudhakar M.</creatorcontrib><creatorcontrib>Dandapani, R.</creatorcontrib><title>Scan Design Using Standard Flip-Flops</title><title>IEEE design & test of computers</title><addtitle>MDT</addtitle><description>Classical scan designs require properly augmented flip-flops, often called scan flip-flops. Problems stem from the high area overhead implied by the need for these flip-flops or the inability to modify standard flip-flops. The authors outline a method to design easily testable sequential circuits that achieve scan designs using standard (unmodified) flip-flops.</description><issn>0740-7475</issn><issn>1558-1918</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1987</creationdate><recordtype>article</recordtype><recordid>eNo9zztPwzAUhmELgUQozAwsWRid-sT3EbUEkIoY2s6Wr1VQSKO4C_-eVKmYznLeT3oQegRSARC9_FzvKtBKVrXmAPwKFcC5wqBBXaOCSEawZJLforucvwkhAEIU6HnrbV-uY24PfbnPbX8otyfbBzuGsunaATfdccj36CbZLseHy12gffO6W73jzdfbx-plg33N9QnXKlBlwSknQboYlGDaKSq8coyKpG1KXjshReTWE8VpLayL0cLUQQqBLtBy3vXjMecxJjOM7Y8dfw0Qc1aaSWnOSjMrp-JpLtoY4_83I0JryugfZnJM-w</recordid><startdate>198702</startdate><enddate>198702</enddate><creator>Reddy, Sudhakar M.</creator><creator>Dandapani, R.</creator><general>IEEE Computer Society</general><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>198702</creationdate><title>Scan Design Using Standard Flip-Flops</title><author>Reddy, Sudhakar M. ; Dandapani, R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c259t-28d38a1b8b717bed8649b836c8b436f9affc9b676e5ac085326abeea18d31fdd3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1987</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Reddy, Sudhakar M.</creatorcontrib><creatorcontrib>Dandapani, R.</creatorcontrib><collection>CrossRef</collection><jtitle>IEEE design & test of computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Reddy, Sudhakar M.</au><au>Dandapani, R.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Scan Design Using Standard Flip-Flops</atitle><jtitle>IEEE design & test of computers</jtitle><stitle>MDT</stitle><date>1987-02</date><risdate>1987</risdate><volume>4</volume><issue>1</issue><spage>52</spage><epage>54</epage><pages>52-54</pages><issn>0740-7475</issn><eissn>1558-1918</eissn><coden>IDTCEC</coden><abstract>Classical scan designs require properly augmented flip-flops, often called scan flip-flops. Problems stem from the high area overhead implied by the need for these flip-flops or the inability to modify standard flip-flops. The authors outline a method to design easily testable sequential circuits that achieve scan designs using standard (unmodified) flip-flops.</abstract><pub>IEEE Computer Society</pub><doi>10.1109/MDT.1987.295115</doi><tpages>3</tpages></addata></record> |
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title | Scan Design Using Standard Flip-Flops |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T16%3A38%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Scan%20Design%20Using%20Standard%20Flip-Flops&rft.jtitle=IEEE%20design%20&%20test%20of%20computers&rft.au=Reddy,%20Sudhakar%20M.&rft.date=1987-02&rft.volume=4&rft.issue=1&rft.spage=52&rft.epage=54&rft.pages=52-54&rft.issn=0740-7475&rft.eissn=1558-1918&rft.coden=IDTCEC&rft_id=info:doi/10.1109/MDT.1987.295115&rft_dat=%3Ccrossref_RIE%3E10_1109_MDT_1987_295115%3C/crossref_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4069934&rfr_iscdi=true |