A 112-Gb/s, -10 dBm Sensitivity, +5 dBm Overload, and SiPh-Based Receiver Frontend in 22-nm FDSOI

This letter demonstrates a Si-Photonic (SiPh)-based 112 Gb/s PAM4 optical receiver frontend using novel single-ended transimpedance amplifier (TIA) architecture that achieves −10 and +5 dBm input optical modulation amplitude (OMA) sensitivity and overload, respectively. To achieve that an overload mitigation circuit is proposed to break the tradeoff between noise and linearity of the shunt feedback CMOS TIAs. The TIA is optimized to provide the best sensitivity and linearity performance at minimum and maximum input OMA, respectively. Implemented in 22-nm FDSOI technology, and designed for 112 Gb/s PAM4 optical links, the TIA achieves more than +15 dBm OMA range with 11 pA/ \surd Hz input referred noise while burning only 155 mW from an 1.8-V supply.