2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications

This letter presents a 2-Mb embedded phase change memory (ePCM) macrocell designed in 90-nm BJT-CMOS-DMOS (BCD) technology able to address the next generation of automotive and smart-power products exploiting an ePCM cell based on a Ge-rich chalcogenide alloy. The optimized memory allows 16-ns rando...

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Veröffentlicht in:	IEEE solid-state circuits letters 2019-09, Vol.2 (9), p.135-138
Hauptverfasser:	Carissimi, M., Mukherjee, R., Tyagi, V., Disegni, F., Manfre, D., Torti, C., Gallinari, D., Rossi, S., Gambero, A., Brambilla, D., Zuliani, P., Zurla, R., Cabrini, A., Torelli, G., Pasotti, M., Auricchio, C., Calvetti, E., Capecchi, L., Croce, L., Zanchi, S., Rana, V., Mishra, P.
Format:	Artikel
Sprache:	eng
Schlagworte:	Access time Automotive applications Automotive engineering Circuits CMOS Computer architecture Data processing embedded memory Endurance Germanium germanium-rich alloy Macrocell networks Microprocessors nonvolatile memory Phase change memory Phase transitions Programming Random access memory Sense amplifiers smart power devices Solid state circuits
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Zusammenfassung:	This letter presents a 2-Mb embedded phase change memory (ePCM) macrocell designed in 90-nm BJT-CMOS-DMOS (BCD) technology able to address the next generation of automotive and smart-power products exploiting an ePCM cell based on a Ge-rich chalcogenide alloy. The optimized memory allows 16-ns random access time and 5-Mbit/s write throughput from -40 °C to 175 °C, with 100 kcycle endurance. The sense amplifier, the programming circuitry, and the data processing logic able to meet automotive requirements are described. The silicon results are provided.
ISSN:	2573-9603 2573-9603
DOI:	10.1109/LSSC.2019.2935874