Multiplierless FIR filter design algorithms

This letter concerns the design of multiplierless implementations of finite impulse response (FIR) filters to achieve minimum adder cost. Existing approaches include dependence-graph multiplier-block methods and Common Subexpression Elimination (CSE) techniques applied either to the Canonic Signed Digit (CSD) representation of the coefficients or to other Signed Digit (SD) representations. We introduce a new CSE algorithm, which searches a bounded number of Minimal Signed Digit (MSD) representations. The performance of existing algorithms and the new algorithm is compared. It is shown that the relative performance of different algorithms depends on filter length and wordlength and that the new algorithm gives significant improvements in some cases.