A Low-Noise W-Band Receiver in a 28-nm CMOS Technology

A passive mixer-first receiver architecture operating at a frequency range between 70 and 86 GHz, together with a two-stage LO buffer and a low noise IF amplifier, is presented and designed in a 28-nm bulk CMOS technology. The receiver achieves a single-sideband noise figure (SSB NF) of less than 10 dB for IF frequencies above 400 kHz with a minimum of 9 dB above 1 MHz. The implemented chip features a voltage gain of about 14 dB and a 1-dB compression point of −5 dBm. The receiver core occupies an area of \mathbf {0.09}~{\text {mm}^{2}} and consumes 55 mA from a 1.8-V power supply including all ON-chip biasing circuits.