A RISC-V-Based High-Throughput Accelerator for Sparse Winograd CNN Inference on FPGA

This paper proposes a RISC-V-based accelerator for inferring a model that uses Efficient Sparse Winograd Convolutional Neural Networks. This accelerator consists of a RISC-V processor (AndesNX27V) and a coprocessor; the latter performs the Winograd-ReLU convolutions and fully connected layers of the network. The pooling and ReLU layers of the network are executed by the processor in parallel with the coprocessor to increase throughput. In addition, on-chip buffers are used for the input/output data and filter weights to ensure pipelined operation. Implemented on an AMD VCU118 FPGA platform operating at 250 MHz, the accelerator achieves an average throughput of 5104.6 GOP/s when inferring a VGG16-based model.