A High-Performance Hardware Accelerator for ECC in GF(p) Over Generic Weierstrass Curves
A 256-bit high-performance hardware accelerator for Elliptic Curve Cryptography (ECC) in GF(p) over Generic Weierstrass Curves is presented in this paper. Firstly, to improve the utilization of the multiplier, a new radix-128 Montgomery modular multiplication (MMM) without final reduction is propose...
Gespeichert in:
| Veröffentlicht in: | IEEE embedded systems letters 2024-12, p.1-1 |
|---|---|
| Hauptverfasser: | , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1 |
|---|---|
| container_issue | |
| container_start_page | 1 |
| container_title | IEEE embedded systems letters |
| container_volume | |
| creator | Xie, Yujun Yan, Riheng Liu, Yuan Zheng, Xin Cai, Shuting Xiong, Xiaoming |
| description | A 256-bit high-performance hardware accelerator for Elliptic Curve Cryptography (ECC) in GF(p) over Generic Weierstrass Curves is presented in this paper. Firstly, to improve the utilization of the multiplier, a new radix-128 Montgomery modular multiplication (MMM) without final reduction is proposed. Secondly, a combined-addition (CA) is proposed to recover the final reduction of MMM. The CA could reduce the clock cycles of continuous MMM. Finally, a high-parallelism Montgomery ladder hardware accelerator is presented to improve the performance of the elliptic curve point-multiplication (ECPM). The proposed accelerator consumes 766k gates and compute the 256-bit ECPM in 0.014 ms on ASIC with a 90 nm standard cell library. This is a higher performance design compared to previous research in GF(p) over Generic Weierstrass Curves. |
| doi_str_mv | 10.1109/LES.2024.3514127 |
| format | Article |
| fullrecord | <record><control><sourceid>crossref_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_LES_2024_3514127</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10804234</ieee_id><sourcerecordid>10_1109_LES_2024_3514127</sourcerecordid><originalsourceid>FETCH-LOGICAL-c624-b528c8f8a992c77e73cbce29809c14bb081b12bee8cb9c0dcc00368dddfac2473</originalsourceid><addsrcrecordid>eNpNkD1LA0EQhhdRMMT0FhZbanFxv-52twxHPoRABAPaHbtzc3qSL2ZjxH_vhQRxmhl432eKh7FbKYZSCv84H78MlVBmqHNppLIXrCe90ZkorLz8uwt9zQYpfYpucmNznffY24jP2veP7Bmp2dI6bAD5LFD9HQj5CABXSGG_Jd6lfFyWvN3w6eR-98AXByQ-xQ1SC_wVW6S0p5ASL7_ogOmGXTVhlXBw3n22nIyX5SybL6ZP5WieQaFMFnPlwDUueK_AWrQaIqDyTniQJkbhZJQqIjqIHkQNIIQuXF3XTQBlrO4zcXoLtE2JsKl21K4D_VRSVEc3VeemOrqpzm465O6EtIj4r-6EUdroXzPDX3E</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>A High-Performance Hardware Accelerator for ECC in GF(p) Over Generic Weierstrass Curves</title><source>IEEE Electronic Library (IEL)</source><creator>Xie, Yujun ; Yan, Riheng ; Liu, Yuan ; Zheng, Xin ; Cai, Shuting ; Xiong, Xiaoming</creator><creatorcontrib>Xie, Yujun ; Yan, Riheng ; Liu, Yuan ; Zheng, Xin ; Cai, Shuting ; Xiong, Xiaoming</creatorcontrib><description>A 256-bit high-performance hardware accelerator for Elliptic Curve Cryptography (ECC) in GF(p) over Generic Weierstrass Curves is presented in this paper. Firstly, to improve the utilization of the multiplier, a new radix-128 Montgomery modular multiplication (MMM) without final reduction is proposed. Secondly, a combined-addition (CA) is proposed to recover the final reduction of MMM. The CA could reduce the clock cycles of continuous MMM. Finally, a high-parallelism Montgomery ladder hardware accelerator is presented to improve the performance of the elliptic curve point-multiplication (ECPM). The proposed accelerator consumes 766k gates and compute the 256-bit ECPM in 0.014 ms on ASIC with a 90 nm standard cell library. This is a higher performance design compared to previous research in GF(p) over Generic Weierstrass Curves.</description><identifier>ISSN: 1943-0663</identifier><identifier>EISSN: 1943-0671</identifier><identifier>DOI: 10.1109/LES.2024.3514127</identifier><identifier>CODEN: ESLMAP</identifier><language>eng</language><publisher>IEEE</publisher><subject>Adders ; Clocks ; Cryptography ; Elliptic curve cryptography ; Elliptic curve point multiplication ; Elliptic curves ; Engines ; Finite element analysis ; Hardware acceleration ; Hardware accelerator ; Memory management ; Montgomery ladder ; Parallel processing</subject><ispartof>IEEE embedded systems letters, 2024-12, p.1-1</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><orcidid>0000-0002-2421-7621 ; 0000-0002-7822-822X ; 0000-0003-4931-9664 ; 0000-0002-7289-2103 ; 0000-0002-2842-6439</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10804234$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10804234$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Xie, Yujun</creatorcontrib><creatorcontrib>Yan, Riheng</creatorcontrib><creatorcontrib>Liu, Yuan</creatorcontrib><creatorcontrib>Zheng, Xin</creatorcontrib><creatorcontrib>Cai, Shuting</creatorcontrib><creatorcontrib>Xiong, Xiaoming</creatorcontrib><title>A High-Performance Hardware Accelerator for ECC in GF(p) Over Generic Weierstrass Curves</title><title>IEEE embedded systems letters</title><addtitle>LES</addtitle><description>A 256-bit high-performance hardware accelerator for Elliptic Curve Cryptography (ECC) in GF(p) over Generic Weierstrass Curves is presented in this paper. Firstly, to improve the utilization of the multiplier, a new radix-128 Montgomery modular multiplication (MMM) without final reduction is proposed. Secondly, a combined-addition (CA) is proposed to recover the final reduction of MMM. The CA could reduce the clock cycles of continuous MMM. Finally, a high-parallelism Montgomery ladder hardware accelerator is presented to improve the performance of the elliptic curve point-multiplication (ECPM). The proposed accelerator consumes 766k gates and compute the 256-bit ECPM in 0.014 ms on ASIC with a 90 nm standard cell library. This is a higher performance design compared to previous research in GF(p) over Generic Weierstrass Curves.</description><subject>Adders</subject><subject>Clocks</subject><subject>Cryptography</subject><subject>Elliptic curve cryptography</subject><subject>Elliptic curve point multiplication</subject><subject>Elliptic curves</subject><subject>Engines</subject><subject>Finite element analysis</subject><subject>Hardware acceleration</subject><subject>Hardware accelerator</subject><subject>Memory management</subject><subject>Montgomery ladder</subject><subject>Parallel processing</subject><issn>1943-0663</issn><issn>1943-0671</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkD1LA0EQhhdRMMT0FhZbanFxv-52twxHPoRABAPaHbtzc3qSL2ZjxH_vhQRxmhl432eKh7FbKYZSCv84H78MlVBmqHNppLIXrCe90ZkorLz8uwt9zQYpfYpucmNznffY24jP2veP7Bmp2dI6bAD5LFD9HQj5CABXSGG_Jd6lfFyWvN3w6eR-98AXByQ-xQ1SC_wVW6S0p5ASL7_ogOmGXTVhlXBw3n22nIyX5SybL6ZP5WieQaFMFnPlwDUueK_AWrQaIqDyTniQJkbhZJQqIjqIHkQNIIQuXF3XTQBlrO4zcXoLtE2JsKl21K4D_VRSVEc3VeemOrqpzm465O6EtIj4r-6EUdroXzPDX3E</recordid><startdate>20241215</startdate><enddate>20241215</enddate><creator>Xie, Yujun</creator><creator>Yan, Riheng</creator><creator>Liu, Yuan</creator><creator>Zheng, Xin</creator><creator>Cai, Shuting</creator><creator>Xiong, Xiaoming</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0000-0002-2421-7621</orcidid><orcidid>https://orcid.org/0000-0002-7822-822X</orcidid><orcidid>https://orcid.org/0000-0003-4931-9664</orcidid><orcidid>https://orcid.org/0000-0002-7289-2103</orcidid><orcidid>https://orcid.org/0000-0002-2842-6439</orcidid></search><sort><creationdate>20241215</creationdate><title>A High-Performance Hardware Accelerator for ECC in GF(p) Over Generic Weierstrass Curves</title><author>Xie, Yujun ; Yan, Riheng ; Liu, Yuan ; Zheng, Xin ; Cai, Shuting ; Xiong, Xiaoming</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c624-b528c8f8a992c77e73cbce29809c14bb081b12bee8cb9c0dcc00368dddfac2473</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Adders</topic><topic>Clocks</topic><topic>Cryptography</topic><topic>Elliptic curve cryptography</topic><topic>Elliptic curve point multiplication</topic><topic>Elliptic curves</topic><topic>Engines</topic><topic>Finite element analysis</topic><topic>Hardware acceleration</topic><topic>Hardware accelerator</topic><topic>Memory management</topic><topic>Montgomery ladder</topic><topic>Parallel processing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Xie, Yujun</creatorcontrib><creatorcontrib>Yan, Riheng</creatorcontrib><creatorcontrib>Liu, Yuan</creatorcontrib><creatorcontrib>Zheng, Xin</creatorcontrib><creatorcontrib>Cai, Shuting</creatorcontrib><creatorcontrib>Xiong, Xiaoming</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE embedded systems letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Xie, Yujun</au><au>Yan, Riheng</au><au>Liu, Yuan</au><au>Zheng, Xin</au><au>Cai, Shuting</au><au>Xiong, Xiaoming</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A High-Performance Hardware Accelerator for ECC in GF(p) Over Generic Weierstrass Curves</atitle><jtitle>IEEE embedded systems letters</jtitle><stitle>LES</stitle><date>2024-12-15</date><risdate>2024</risdate><spage>1</spage><epage>1</epage><pages>1-1</pages><issn>1943-0663</issn><eissn>1943-0671</eissn><coden>ESLMAP</coden><abstract>A 256-bit high-performance hardware accelerator for Elliptic Curve Cryptography (ECC) in GF(p) over Generic Weierstrass Curves is presented in this paper. Firstly, to improve the utilization of the multiplier, a new radix-128 Montgomery modular multiplication (MMM) without final reduction is proposed. Secondly, a combined-addition (CA) is proposed to recover the final reduction of MMM. The CA could reduce the clock cycles of continuous MMM. Finally, a high-parallelism Montgomery ladder hardware accelerator is presented to improve the performance of the elliptic curve point-multiplication (ECPM). The proposed accelerator consumes 766k gates and compute the 256-bit ECPM in 0.014 ms on ASIC with a 90 nm standard cell library. This is a higher performance design compared to previous research in GF(p) over Generic Weierstrass Curves.</abstract><pub>IEEE</pub><doi>10.1109/LES.2024.3514127</doi><tpages>1</tpages><orcidid>https://orcid.org/0000-0002-2421-7621</orcidid><orcidid>https://orcid.org/0000-0002-7822-822X</orcidid><orcidid>https://orcid.org/0000-0003-4931-9664</orcidid><orcidid>https://orcid.org/0000-0002-7289-2103</orcidid><orcidid>https://orcid.org/0000-0002-2842-6439</orcidid></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1943-0663 |
| ispartof | IEEE embedded systems letters, 2024-12, p.1-1 |
| issn | 1943-0663 1943-0671 |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_LES_2024_3514127 |
| source | IEEE Electronic Library (IEL) |
| subjects | Adders Clocks Cryptography Elliptic curve cryptography Elliptic curve point multiplication Elliptic curves Engines Finite element analysis Hardware acceleration Hardware accelerator Memory management Montgomery ladder Parallel processing |
| title | A High-Performance Hardware Accelerator for ECC in GF(p) Over Generic Weierstrass Curves |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T15%3A00%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20High-Performance%20Hardware%20Accelerator%20for%20ECC%20in%20GF(p)%20Over%20Generic%20Weierstrass%20Curves&rft.jtitle=IEEE%20embedded%20systems%20letters&rft.au=Xie,%20Yujun&rft.date=2024-12-15&rft.spage=1&rft.epage=1&rft.pages=1-1&rft.issn=1943-0663&rft.eissn=1943-0671&rft.coden=ESLMAP&rft_id=info:doi/10.1109/LES.2024.3514127&rft_dat=%3Ccrossref_RIE%3E10_1109_LES_2024_3514127%3C/crossref_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=10804234&rfr_iscdi=true |