A High-Performance Hardware Accelerator for ECC in GF(p) Over Generic Weierstrass Curves

A 256-bit high-performance hardware accelerator for Elliptic Curve Cryptography (ECC) in GF(p) over Generic Weierstrass Curves is presented in this paper. Firstly, to improve the utilization of the multiplier, a new radix-128 Montgomery modular multiplication (MMM) without final reduction is proposed. Secondly, a combined-addition (CA) is proposed to recover the final reduction of MMM. The CA could reduce the clock cycles of continuous MMM. Finally, a high-parallelism Montgomery ladder hardware accelerator is presented to improve the performance of the elliptic curve point-multiplication (ECPM). The proposed accelerator consumes 766k gates and compute the 256-bit ECPM in 0.014 ms on ASIC with a 90 nm standard cell library. This is a higher performance design compared to previous research in GF(p) over Generic Weierstrass Curves.