Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic

The posit number system represents a binary numerical format devised primarily to mitigate the shortcomings of the IEEE 754 floating-point standard commonly used in modern computer arithmetic. Unlike IEEE 754, which utilizes a fixed-width representation, posits offer a variable-size encoding, dynamically adjusting the number of bits allocated based on the magnitude of the represented number. This adaptability enables posits to provide enhanced precision across a broader range of values, addressing issues like gradual underflow and the multiple representations of zero and NaN values inherent in IEEE 754. However, the dynamic bit allocation also poses significant challenges in decoding the posit number into its constituent fields and packing back the fields of the resultant posit once the arithmetic operations have been performed. For posits to become a viable alternative to floating-points in practical computing systems, the decoding and encoding overheads of posits need to be minimized. Hence, the aim of this paper is to develop energy-efficient hardware for posit decoding and encoding. The proposed < 16, 2 > posit decoders, Decoder A and Decoder B show an improvement of over 65% and 33% compared to literature in terms of energy requirements. Similarly, the proposed < 16, 2 > encoder circuit is over 52% more energy-efficient than existing encoder circuits.