Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs

Field-programmable gate arrays (FPGAs) are known to increase performance and energy efficiency of parallel applications. Integrated on multiprocessor systems-on-chip, they can be used as accelerators in addition to the multicore processor. However, state-of-the-art high-level synthesis tools require an intensive manual effort to make effective use of all available FPGA resources. This letter proposes an automatic hardware/software partitioning software tool which optimizes for different design goals, such as performance and power. A given source code is analyzed and all necessary decisions and annotations are performed without the need for designer interaction. Further, abstract but accurate power models for FPGA and processor enable power or energy driven optimization. The tool flow is tested against representative benchmarks on the Xilinx Zynq UltraScale+. On average, an energy reduction of 71 % is possible compared to a nonpartitioned, sequential execution.